Interconnect Schemes for Low Inductance Ceramic Capacitors
Written By: Jeff Cain, Ph.D.
Abstract:
As digital electronic systems continue to operate at higher and higher frequencies, the use of low inductance decoupling capacitors continues to increase. The parasitic inductance of the devices themselves is important, but the method used to connect the components to the system, such as printed circuit boards (PCB), is also a considerable factor. Adding inductance in the connection scheme can eliminate some of the effectiveness of the use of these low inductance elements. This paper will examine some of the different schemes utilized at the board level to minimize the loop inductance of the decoupling capacitors.
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As digital electronic systems continue to operate at higher and higher frequencies, the use of low inductance decoupling capacitors continues to increase. The parasitic inductance of the devices themselves is important, but the method used to connect the components to the system, such as printed circuit boards (PCB), is also a considerable factor. Adding inductance in the connection scheme can eliminate some of the effectiveness of the use of these low inductance elements. This paper will examine some of the different schemes utilized at the board level to minimize the loop inductance of the decoupling capacitors.
