Parameters Important For Surface Mount Applications Of Multilayer Ceramic Capacitors
Written By: Bharat S. Rawal | Kumar Krishnamani | John Maxwell
Abstract:
With increasing use of multilayer ceramic capacitors (MLCs) in surface mount technology (SMT), the understanding of the mechanical properties and thermal stress resistance parameters of MLCs is essential for zero defect soldering and sub ppm failure rates. In this paper, various aspects of SMT including zero defect design, placement considerations, soldering techniques, thermal stress resistance parameters, and post solder handling are reviewed. Special emphasis is given to parameters responsible for thermal shock behavior of MLCs with review of the effect of overall component thickness, temperature gradients, and terminations of MLCs.
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With increasing use of multilayer ceramic capacitors (MLCs) in surface mount technology (SMT), the understanding of the mechanical properties and thermal stress resistance parameters of MLCs is essential for zero defect soldering and sub ppm failure rates. In this paper, various aspects of SMT including zero defect design, placement considerations, soldering techniques, thermal stress resistance parameters, and post solder handling are reviewed. Special emphasis is given to parameters responsible for thermal shock behavior of MLCs with review of the effect of overall component thickness, temperature gradients, and terminations of MLCs.
